PaxQubit · PyeongJeong Technology Co., Ltd.
From NAND to Qubits.
Hardened, standards-compliant error-correction & encryption IP — FPGA & ASIC ready, built by the engineers who design storage silicon.
One vendor, the full coding-theory spectrum
Error correction, cryptography, and quantum — under one roof
BCH · QC-LDPC
Deterministic and soft-decision error correction for NAND, SSD and communications.
AES-256 · PBKDF2
Standards-compliant encryption and key derivation for data at rest and in flight.
qLDPC
Real-time syndrome decoding for quantum error correction.
IP Catalog
Silicon-grade IP cores, ready to license
64-bit BCH ECC IP Core
Pick a correction strength and sector size — get drop-in Verilog RTL. Baseline 64-bit BCH ECC, configurable up to t=156.
QC-LDPC ECC IP Core (PAX_LDPC)
Inner LDPC + outer BCH + CRC32 targeting UBER < 1e-15. One rate-compatible architecture covers TLC and QLC by parameters only.
AES-256 Encryption IP Core
Standards-compliant AES-256 for data-at-rest (XTS) and data-in-flight (GCM). Roadmap — contact us for early access.
PBKDF2-HMAC Key-Derivation IP Core
RFC 8018 PBKDF2-HMAC in hardware. Midstate-cached SHA-256 core, AXI4-Lite, tunable work factor — pairs with AES-XTS for a full secure-storage datapath.
qLDPC Decoder IP Core
Bringing classical LDPC decoding expertise to quantum error correction — a real-time syndrome decoder for qLDPC codes. Early-access / research collaboration.
Storage Security Stack
A single datapath, key unwrap to NAND protection
PaxQubit ships every block of the secure-storage datapath — no multi-vendor integration.
PBKDF2
Unwraps the media key from a passphrase
AES-256-XTS
Encrypts data sector by sector
BCH / QC-LDPC
Corrects NAND bit errors
Why PaxQubit
From authentication to device lifetime
Brute-force-resistant keys
PBKDF2-HMAC key stretching (salt + tunable iterations) — ~0.1 s for the user, years for an attacker. RFC 8018 / NIST SP 800-132.
One-vendor secure storage
PBKDF2 → AES-XTS → BCH/LDPC, with the SHA core shared for eMMC RPMB — one vendor, less area and verification.
Longer NAND lifetime
Soft-decision QC-LDPC and high-strength BCH extend TLC/QLC NAND endurance and retention margins, keeping drives in service longer.
Silicon-grade & compliant
FPGA & ASIC-ready RTL aligned to FIPS, NIST, IEEE 1619, 3GPP and JEDEC.
Standards & compliance targets
Need a core for your controller or SoC?
Tell us your target device and correction/throughput goals. We respond within one business day.
Request Quote / Eval