PBKDF2-HMAC Key-Derivation IP Core

Hardware PBKDF2-HMAC-SHA-256/512 key derivation for SSD/eMMC key establishment.

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≈0.10 s

Key derivation, c=100,000 @ 150 MHz

~3–5K LE

Logic on Arria II GX (≈2% of EP2AGX260)

2×

Midstate cache halves SHA work per iteration

Overview

A hardware PBKDF2-HMAC engine that turns a user password into a cryptographic key with two defenses — a per-record salt and a tunable iteration count (key stretching). It is built for storage controllers: deriving the Key-Encryption-Key (KEK) that unlocks an SSD/eMMC, host authentication, and preparing data-encryption keys.

The design decomposes into three layers, but the only arithmetic datapath is a single SHA-256 compression core — the HMAC and PBKDF2 layers are pure control FSMs. A midstate cache pre-computes the password-key padding once and reuses it across every iteration, so one iteration costs just two SHA-256 block compressions (roughly a 2× saving). The same SHA-256/HMAC core is reused for eMMC RPMB authentication.

Block Diagram

Parametric specification

Role	SSD/eMMC controller key derivation (KEK), host auth, data-key prep
Standards	RFC 8018 (PBKDF2), RFC 2104 (HMAC), FIPS 180-4 (SHA-2), NIST SP 800-132
Algorithm	PBKDF2-HMAC-SHA-256 (SHA-512 option)
PRF	HMAC-SHA-256 / HMAC-SHA-512
Iteration count (work factor)	tunable, 32-bit (e.g. 600,000 per OWASP 2023)
Derived key length	up to 64 B (multi-block for larger)
Interface	AXI4-Lite slave (32-bit); APB4 via bridge; IRQ or polling
Key optimization	midstate cache → 1 iteration = 2 SHA-256 compressions
Clock	100–150 MHz (Arria II GX)
Resource	≈3,000–5,000 LE on EP2AGX260 (≈2%)
Verification	layered KAT: SHA-256, HMAC (RFC 4231), PBKDF2 vectors
Implementation	pure RTL (vendor-primitive-free); iverilog + Quartus
Status	Design spec Rev 1.1, RTL deliverable; FPGA characterization at integration

Performance

≈0.10 s

Key derivation, c=100,000 @ 150 MHz

~3–5K LE

Logic on Arria II GX (≈2% of EP2AGX260)

2×

Midstate cache halves SHA work per iteration

Variants

PBKDF2-SHA256

Default — HMAC-SHA-256 PRF, 32 B hash, mainstream KEK derivation.

PBKDF2-SHA512

Higher-strength option — HMAC-SHA-512 PRF, 64 B hash.

Deliverables

Synthesizable Verilog RTL (sha256_core, hmac_engine, pbkdf2_engine, AXI4-Lite regs, top) — pure RTL, vendor-primitive-free
AXI4-Lite register map + bare-metal C driver (polling & interrupt)
Layered KAT testbench (SHA-256, HMAC RFC 4231, PBKDF2 vectors) + iverilog flow
Quartus synthesis scripts and design specification Rev 1.1 (under NDA)

Supported Devices

Intel/Altera Arria II GX (EP2AGX260, Quartus 20.1)ASIC — process-portable pure RTL

Targets / verified platforms. ASIC process numbers are characterized at integration.

Full secure-storage datapath from one vendor: PBKDF2 derives the KEK and unwraps the media key (MEK), AES-256-XTS encrypts the sectors (IEEE 1619), and the shared SHA-256/HMAC core authenticates eMMC RPMB (JEDEC) — saving area and verification effort.

Resource and timing figures are estimates on Arria II GX (EP2AGX260); final numbers are characterized at integration. The detailed register map, C driver and test vectors are provided under NDA.

Documents

Full datasheet, integration guide and evaluation files are available under NDA. Request access below — we reply within one business day.

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Applications

SSD / eMMC self-encrypting drive (SED) KEK derivation

Secure boot / firmware key derivation

Host authentication & data-at-rest key prep

eMMC RPMB authentication (shared HMAC-SHA-256 core)

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