Error Correction
QC-LDPC ECC IP Core (PAX_LDPC)
Soft-decision QC-LDPC for 3D NAND TLC/QLC SSD controllers.
Overview
PAX_LDPC is a quasi-cyclic LDPC error-correction core for 3D NAND SSD controllers. It concatenates an inner soft-decision QC-LDPC code with an outer BCH (t=8) and a CRC32 placed inside the protected region, targeting an uncorrectable bit-error rate below 1e-15.
A two-tier decoder runs a low-power hard bit-flipping pass first and escalates only the residual codewords to a soft layered normalized-min-sum decoder, with syndrome-zero early termination. Migrating from TLC to QLC is a parameter change (Z / kb / mb) — the same RTL covers all three operating rates.
Block Diagram
Parametric specification
| Role | 3D NAND TLC/QLC SSD controller ECC |
|---|---|
| Code | Quasi-cyclic LDPC, lifting factor Z = 256 |
| Concatenation | inner QC-LDPC + outer BCH (t=8) + CRC32 |
| Code rate | 0.897 (TLC) · 0.844 / 0.802 (QLC) |
| N / K (TLC) | N = 37,120 · K = 33,280 |
| Decoder | 2-tier: hard bit-flip → soft layered NMS, syndrome=0 early termination |
| Data unit | 4 KB + meta (16 B) + CRC32 |
| Code construction | PEG2 gap-parity, girth ≥ 6, degree-1 nodes = 0 |
| Interfaces | APB config · valid/ready data[63:0] · UE/tier/iter status |
| Target UBER | < 1e-15 (with outer BCH + CRC32) |
| Status | TLC FPGA-verified (pre-production); QLC RTL-complete, synthesis FIT |
Performance
Variants
PAX_LDPC-TLC
Rate 0.897 baseline — 3D NAND TLC, FPGA-verified on Kintex-7.
PAX_LDPC-QLC
Rate 0.844 / 0.802 — QLC fresh-to-worst-case, parameter-only retarget.
Deliverables
- Verilog-2001 RTL (RU encoder, compressed-BRAM min-sum core, bit-flip tier, LDPC+BCH+CRC32 hybrid top)
- Golden Python model + channel/decoder/floor simulations
- Five testbenches (encoder, decoder, stress, wrappers)
- Vivado / Quartus synthesis scripts, H-matrix files, parameter headers
- Development reports & design docs (under NDA)
Supported Devices
Targets / verified platforms. ASIC process numbers are characterized at integration.
FPGA resource and error-floor figures are out-of-context synthesis / importance-sampling estimates on a dev board (xc7k160t), not silicon-measured guarantees. Correction-cliff figures are simulation upper bounds.
Pin/interface compatible with the BCH ECC core, so a controller can move from BCH to LDPC without re-plumbing the datapath.
Documents
Full datasheet, integration guide and evaluation files are available under NDA. Request access below — we reply within one business day.
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