IP Catalog

IP Core Catalog

Parametric error-correction and cryptographic IP for NAND/SSD controllers, communications, and secure systems. Headline specs below; full datasheets on request.

Error Correction IP

Best-seller

Error Correction

64-bit BCH ECC IP Core

Pick a correction strength and sector size — get drop-in Verilog RTL. Baseline 64-bit BCH ECC, configurable up to t=156.

t8t16t32t48t64t96t120t128

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Featured

Error Correction

QC-LDPC ECC IP Core (PAX_LDPC)

Inner LDPC + outer BCH + CRC32 targeting UBER < 1e-15. One rate-compatible architecture covers TLC and QLC by parameters only.

QC-LDPC · Z=256 · rate 0.897 / 0.844 / 0.802 · 2-tier decoder

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NewResearch

Error Correction

qLDPC Decoder IP Core

Bringing classical LDPC decoding expertise to quantum error correction — a real-time syndrome decoder for qLDPC codes. Early-access / research collaboration.

qLDPC · BP / BP+OSD · real-time syndrome decode

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Security & Crypto IP

Coming soon

Security & Crypto

AES-256 Encryption IP Core

Standards-compliant AES-256 for data-at-rest (XTS) and data-in-flight (GCM). Roadmap — contact us for early access.

AES-256 · XTS / GCM / CBC / CTR · FIPS-197

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Featured

Security & Crypto

PBKDF2-HMAC Key-Derivation IP Core

RFC 8018 PBKDF2-HMAC in hardware. Midstate-cached SHA-256 core, AXI4-Lite, tunable work factor — pairs with AES-XTS for a full secure-storage datapath.

PBKDF2 · HMAC-SHA-256/512 · AXI4-Lite · RFC 8018

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Parametric comparison

IP Core Catalog

IP Core	Standard / Role	Key configuration	Target	Status
BCH-t8	NAND/SSD ECC · shortened BCH codec	t=8 · 14 B parity · 1 KB	FPGA / ASIC	RTL-complete	Request Quote
BCH-t16	NAND/SSD ECC · shortened BCH codec	t=16 · 28 B parity · 1 KB	FPGA / ASIC	RTL-complete	Request Quote
BCH-t32	NAND/SSD ECC · shortened BCH codec	t=32 · 56 B parity · 1 KB	FPGA / ASIC	RTL-complete	Request Quote
BCH-t48	NAND/SSD ECC · shortened BCH codec	t=48 · 84 B parity · 1 KB	FPGA / ASIC	RTL-complete	Request Quote
BCH-t64 Baseline	NAND/SSD ECC · shortened BCH codec	t=64 · 112 B parity · 1 KB	FPGA / ASIC	RTL-complete	Request Quote
BCH-t96	NAND/SSD ECC · shortened BCH codec	t=96 · 168 B parity · 1 KB	FPGA / ASIC	RTL-complete	Request Quote
BCH-t120	NAND/SSD ECC · shortened BCH codec	t=120 · 210 B parity · 1 KB	FPGA / ASIC	RTL-complete	Request Quote
BCH-t128	NAND/SSD ECC · shortened BCH codec	t=128 · 224 B parity · 1 KB	FPGA / ASIC	RTL-complete	Request Quote
QC-LDPC ECC IP Core (PAX_LDPC) Featured	3D NAND TLC/QLC SSD ECC · concatenated QC-LDPC	rate 0.897 (TLC) / 0.844 / 0.802 (QLC), Z=256	FPGA (verified) / ASIC	FPGA-verified	Request Quote
AES-256 Encryption IP Core Coming soon	FIPS-197 · SP 800-38A/D/E · IEEE 1619	256-bit key, XTS / GCM / CBC / CTR modes	FPGA / ASIC	Roadmap	Request Quote
PBKDF2-HMAC Key-Derivation IP Core Featured	RFC 8018 / RFC 2104 · FIPS 180-4 · NIST SP 800-132	PBKDF2-HMAC-SHA-256/512, tunable iteration count, AXI4-Lite	FPGA / ASIC	RTL-complete	Request Quote
qLDPC Decoder IP Core NewResearch	Quantum error correction · qLDPC syndrome decode	BP / BP+OSD, bivariate-bicycle codes	FPGA / research	Roadmap	Request Quote

Full datasheet, integration guide and evaluation files are available under NDA. Request access below — we reply within one business day.